ICS9148-11 Datasheet, PDF (3/14 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUMTM

ICS9148 - 11
Power-On Conditions
MODE
1
0
PIN #
44, 43, 41, 40
38, 37, 35, 34,
32, 31, 21, 20,
18, 17, 29, 28
8, 10, 11,
12, 14, 15, 7
28
29
31
7
44, 43, 41, 40
38, 37, 35,
34, 32, 21,
20, 18, 17
8, 10, 11,
12, 14, 15
DESCRIPTION
CPUCLKs
SDRAM
FUNCTION
66.6 MHz - w/serial config enable/disable
66.6 MHz - All SDRAM outputs
PCICLKs
PCI_STOP#
CPU_STOP#
SDRAM/PWR
_DWN#
PCICLK_F
CPUCLKs
SDRAM
PCICLKs
33.3 MHz - w/serial config enable/disable
Power Management, PCI (0:5) Clocks Stopped
when low
Power Management, CPU (0:3) Clocks Stopped
when low
Used as PWR_DWN# when low
33.3 MHz - 33.3 MHz - PCI Clock Free running for
Power Management
66.6 MHz - CPU Clocks w/external Stop Control and
serial config individual enable/disable.
66.6 MHz - SDRAM Clocks w/serial config individual
enable/disable.
33.3 MHz - PCI Clocks w/external Stop control and
serial config individual enable/disable.
Example:
a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively.
b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.
Power-On Default Conditions
At power-up and before device programming, all clocks will default to an enabled and “on” condition. The frequencies that are then
produced are on the FS and MODE pin as shown in the table below.
CLOCK
REF 0
IOAPIC (0:1)
DEFAULT CONDITION AT POWER-UP
14.31818 MHz
14.31818 MHz
3