English
Language : 

ICS9148-11 Datasheet, PDF (7/14 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUMTM
◁
ICS9148 - 11
Byte 5: Peripheral Clock Register
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
46
47
-
-
-
2
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 IOAPIC1 (Act/Inact)
1 IOAPIC0 (Act/Inact)
1 Reserved
1 Reserved
1 Reserved
1 REF0(Act/Inact)
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Byte 6: Optional Register for Future
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
Power Management
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK
PCICLK
Other Clocks,
SDRAM,
REF,
IOAPICs
Crystal
VCOs
X
X
0
Low
Low
Stopped
Off
Off
0
0
1
Low
Low
Running
Running
Running
0
1
1
Low
33.3 MHz
Running
Running
Running
1
0
1
66.6 MHz
Low
Running
Running
Running
1
1
1
66.6 MHz
33.3 MHz
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. The first clock pulse coming out
of a stopped clock condition may be slightly distorted due to clock network chargingcircuitry. Board routing and signal loading may have a
large impact on the initial clock distortion also.
ICS9148-11 Power Management Requirements
SIGNAL
CPU_ STOP#
PCI_STOP#
PWR_DWN#
SIGNAL STATE
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1 (Enabled)1
1 (Normal Operation)3
0 (Power Down)4
Latency
No. of rising edges of free
running PCICLK
1
1
1
1
3mS
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
7
 ▷