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ICS8737-11 Datasheet, PDF (8/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1/÷2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 9 shows how the differential input can be wired to accept single end levels. The reference voltage V_REF ~
VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to
the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input
voltage swing. For example, if the input clock swing is only 12.5V and VCC = 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
CLK_IN
C1
0.1uF
V
CC
R1
1K
+
V_REF
-
R2
1K
FIGURE 9 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
8737AG-11
www.icst.com/products/hiperclocks.html
8
REV. A JULY 13, 2001