ICS8737-11 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – LOW SKEW ÷1/÷2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8737-11
LOW SKEW ÷1/÷2
DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
TABLE 4D. LVPECL DC CHARACTERISTICS, V_CC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
I
Input High Current
IH
V_IN = V_CC = 3.465V
V_IN = V_CC = 3.465V
I_IL
Input Low Current
V_IN = 0V, V_CC = 3.465V
V = 0V, V = 3.465V
IN
CC
-5
-150
V_PP
Peak-to-Peak Input Voltage
0.3
V_CMR
Common Mode Input Voltage; NOTE 1, 2
V_EE + 1.5
V_OH
Output High Voltage; NOTE 3
V_CC - 1.4
V_OL
Output Low Voltage; NOTE 3
V_CC - 2.0
V_SWING Peak-to-Peak Output Voltage Swing
0.65
NOTE 1: Common mode voltage is defined as V_IH.
W ^{NOTE 2: For single ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.}
NOTE 3: Outputs terminated with 50 to V_CC - 2V.
Maximum
150
5
1
V_CC
V_CC - 1.0
V_CC - 1.7
0.9
Units
µA
µA
µA
µA
V
V
V
V
V
TABLE 5. AC CHARACTERISTICS, V_CC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
f_MAX
Maximum Output Frequency
CLK, nCLK
1.3
t_PD
Propagation Delay; NOTE 1
PCLK, nPCLK
ģ 650MHz
1.2
650
MHz
1.7
ns
1.6
tsk(o) Output Skew; NOTE 2, 4
60
ps
tsk(b) Bank Skew; NOTE 4
Bank A
Bank B
20
ps
35
tsk(pp) Part-to-Part Skew; NOTE 3, 4
200
ps
t_R
Output Rise Time
t_F
Output Fall Time
odc
Output Duty Cycle
20% to 80% @ 50MHz 300
700
ps
20% to 80% @ 50MHz 300
700
ps
48
50
52
%
All parameters measured at 500MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8737AG-11
www.icst.com/products/hiperclocks.html
5
REV. A JULY 13, 2001