ICS1567 Datasheet, PDF (8/11 Pages) Integrated Circuit Systems – Differential Output Video Dot Clock Generator

ICS1567
AC Characteristics
PARAMETER
Duty Cycle
Frequency Error
Rise Time
Fall Time
VCO Frequency
PLL Acquire Time
Duty Cycle
Load Frequency
Rise Time
Fall Time
Crystal Frequency
Crystal Oscillator
Loading Capacitance
XTAL1 High Time
XTAL1 Low Time
Rise Time
Fall Time
Frequency Select Setup Time
Frequency Select Hold Time
Strobe Pulse Width
Reset Activation
Reset Duration
Restart Delay
SYMBOL
MIN
TYP
CLK and CLK TIMING
THIGH
40
Tr
Tf
FVCO
TLOCK
20
500
LD* TIMING
THIGH
40
FLOAD
Tr
Tf
REFERENCE INPUT CLOCK
FXTAL
5
CPAR
20
TXHI
TXLO
Tr
Tf
8
8
DIGITAL INPUTS
1
10
2
10
3
20
PIPELINE DELAY RESET
4
5
4*TCLK
6
-1*TCLK
MAX
60
0.5
2
2
180
60
60
2
2
20
10
10
2*TCLK
+1.5*TCLK
UNITS
%
%
ns
ns
MHz
uS
%
MHz
ns
ns
MHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
3, 4, 9
5, 9
5, 9
1
6
7, 8
7, 8
2
2
2, 7
2, 7
10
10
10
10
10
10
Notes:
1. Use of the post-divider is required for frequencies lower than 20 MHz on CLK and CLK outputs. Use of the
post-divider is recommended for output frequencies lower than 65 MHz.
2. Values for XTAL1 driven by an external clock
3. Duty Cycle for Differential Output (CLK- CLK)
4. Duty cycle measured at VOD/2 for Differential CLK Output
5. Rise and fall time between 20% and 80% of VOD
6. Duty cycle measured at 1.4V for TTL I/O
7. Rise and fall time between 0.8 and 2.0 VDC for TTL I/O
8. Output pin loading = 15 pF
9. See Figure 3.
10. See Figure 4.
8