ICS1567 Datasheet, PDF (5/11 Pages) Integrated Circuit Systems – Differential Output Video Dot Clock Generator

ICS1567
Load Clock Divider
The ICS1567 has an additional programmable divider that is
used to generate the LOAD frequency. The modulus of this
divider may be set to 3, 4, 5, 6, 8, or 10. The design of this
divider permits the output duty factor to be 50/50, even when
an odd modulus is selected.
The selection of the modulus is done by the ROM look-up
table. A different modulus may, therefore, be selected for each
frequency address.
Pipeline Delay Reset Function
The ICS1567 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This se-
quence is automatically generated by the ICS1567 upon any
rising edge of the STROBE line.
Application Information
Power Supplies
The ICS1567 has two VSS pins to reduce the effects of package
inductance. Both pins are connected to the same potential on
the die (the ground bus). BOTH of these pins should connect
to the ground plane of the video board as close to the package
as is possible.
The ICS1567 has two VDDO pins which are the supply of +5
volt power to all output stages. Again, both VDDO pins connect
to the same point on the die. BOTH of these pins should be
connected to the power plane (or bus) using standard high-fre-
quency decoupling practice. This decoupling consists of a low
series inductance bypass capacitor, using the shortest leads
possible, mounted close to the ICS1567.
When the frequency select inputs (FS0-FS4) are used in a
transparent mode, simply lower and raise the STROBE line to
activate the function. When the frequency select inputs are
latched, simply load the same frequency into the ICS1567
twice.
When changing frequencies, it is advisable to allow 500uSec
after the new frequency is selected to activate the reset func-
tion. The output frequency of the synthesizer should be stable
enough at that point for the RAMDAC to correctly execute its
reset sequence.
See Figure 4 for a diagram of the clock sequencing.
Output Stage Description
The CLK and CLK outputs are each connected to the drains of
P-Channel MOSFET devices. The source of each of these
devices is connected to VDDO. Typical on resistance of each
device is 15 Ohms. These outputs will drive the clock and clock
of a RAMDAC device when a resistive network equivalent to
Figure 3 is utilized.
The LD output is a high-current CMOS type drive whose
frequency is controlled by a programmable divider that may be
selected for a modulus of 3, 4, 5, 6, 8, or 10. Under control of
the ROM, this output may also be suppressed (logic low level)
at any frequency select address, if desired.
The VDD pin is the power supply for the synthesizer circuitry
and other lower current digital functions. We recommend that
RC decoupling or zener regulation be provided for this pin (as
shown in the recommended application circuitry). This will
allow the PLL to “track” through power supply fluctuations
without visible effects.
Crystal Oscillator and Crystal Selection
The ICS1567 has circuitry on-board to implement a Pierce
oscillator with the addition of only one external component, a
quartz crystal. Pierce oscillators operate the crystal in anti- (also
called parallel-) resonant mode. See the AC Characteristics for
the effective capacitive loading to specify when ordering crys-
tals.
So-called series-resonant crystals may also be used with the
ICS1567. Be aware that the oscillation frequency will be
slightly higher than the frequency that is stamped on the can
(typically 0.005-0.01%).
As the entire operation of the phase-locked loop depends on
having a stable reference frequency, we recommend that the
crystal be mounted as closely as possible to the package. Avoid
routing digital signals or the ICS1567 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
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