ICS1567 Datasheet, PDF (3/11 Pages) Integrated Circuit Systems – Differential Output Video Dot Clock Generator

Typical Output Configuration
ICS1567
Notes:
CLK & CLK outputs are pseudo-ECL. Logic low level is set by the ratio of the resistors stacked across the power supply
VLO = (V supply • 160)/(110 +160) in the example shown above.
The above values are a good starting point for RAMDAC or clock generator interface.
Figure 3
Pin Description
PIN NUMBER
1
2
3
4
PIN SYMBOL
• FS0
XTAL1
XTAL2
• STROBE
5
VSS
6
VSS
7
LD
8
• FS4
9
CLK
10
CLK
11
VDDO
12
VDDO
13
VDD
14
• FS3
15
• FS2
16
• FS1
• = inputs with internal pull-up resistor
TYPE
IN
IN
OUT
IN
--
--
OUT
IN
OUT
OUT
--
--
--
IN
IN
IN
DESCRIPTION
Frequency Select LSB.
Crystal Interface/External Oscillator Input.
Crystal Interface.
Control For Frequency Select Latch, also performs automatic
RAMDAC reset.
Device Ground (Both pins must be connected.)
Device Ground (Both pins must be connected.)
Load Output. This output is at CLK frequency divided by N1.
Frequency Select MSB.
Clock Output Inverted.
Clock Output Non-Inverted.
Output Stage Power (Both pins must be connected).
Output Stage Power (Both pins must be connected).
PLL System Power.
Frequency Select.
Frequency Select.
Frequency Select.
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