9DBU0231 Datasheet, PDF (8/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0231 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
PLL Bandwidth
BW
-3dB point in High BW Mode (100MHz)
2.2
3.6
4.8
MHz
1,5
-3dB point in Low BW Mode (100MHz)
1
1.6
2.5
MHz
1,5
PLL Jitter Peaking
t_JPEAK
Peak Pass band Gain (100MHz)
1.3
2.5
dB
1
Duty Cycle
t_DC
Measured differentially, PLL Mode
45
50.2
55
%
1
Duty Cycle Distortion
t_DCD Measured differentially, Bypass Mode @100MHz -1
-0.5
0
%
1,3
Skew, Input to Output
t_pdBYP
t_pdPLL
Bypass Mode, V_T = 50%
PLL Mode V_T = 50%
3400
4300
5200
ps
1
0
50
150
ps
1,4
Skew, Output to Output
Jitter, Cycle to cycle
t_sk3
t_jcyc-cyc
V_T = 50%
PLL mode
Additive Jitter in Bypass Mode
37
50
24.1
50
0.1
5
ps
1,4
ps
1,2
ps
1,2
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
4 _{All outputs at default slew rate}
5 _{The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.}
Electrical Characteristics–Phase Jitter Parameters
TA = T_AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Phase Jitter, PLL Mode
Additive Phase Jitter,
Bypass Mode
SYMBOL
t_jphPCIeG1
t_jphPCIeG2
t_jphPCIeG3
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
t_jphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
t_jphPCIeG1
t_jphPCIeG2
t_jphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
t_{jph125M0 rollover < 1.5MHz, -40db/decade rolloff > 10MHz}
MIN
TYP
30
0.9
2.1
0.5
0.5
0.1
0.1
0.1
0.2
200
MAX
58
1.4
2.6
0.6
0.6
5
0.5
0.3
0.3
300
INDUSTRY
LIMIT UNITS Notes
86 ps (p-p) 1,2,3,5
3
ps _1,2,3,5
(rms)
3.1
ps _1,2,3,5
(rms)
1
ps _1,2,3,5
(rms)
ps
0.7
(rms) ^1,2,3,5
N/A ps (p-p) 1,2,3,5
N/A
ps 1,2,3,4,
(rms) 5
N/A
ps _1,2,3,4
(rms)
N/A
ps _1,2,3,4
(rms)
fs
N/A
(rms) ^1,6
t_jph125M1
125MHz, 12KHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
313
350
N/A
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]}
5 _{Driven by 9FGU0831 or equivalent}
6 _{Rohde&Schartz SMA100}
fs
1,6
(rms)
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
8
REVISION D 04/22/15