9DBU0231 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – slew rate for each output

9DBU0231 DATASHEET
Pin Configuration
FB_DNC# 1
VDDR1.5 2
CLK_IN 3
CLK_IN# 4
GNDR 5
GNDDIG 6
24 23 22 21 20 19
9DBU0231
epad is Gnd
18 DIF1#
17 DIF1
16 VDDA1.5
15 GNDA
14 DIF0#
13 DIF0
7 8 9 10 11 12
SMBus Address Selection Table
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND
pull down resistor (biased to VDD/2)
v prefix indicates internal 120KOhm pull down
resistor
Address
1101101
+ Read/Write bit
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
True O/P Comp. O/P
PLL
0
X
X
X
Low
Low
Off
1
Running
0
X
Low
Low
On¹
1
Running
1
0
Running
Running
On¹
1
Running
1
1
Low
Low
On¹
1. If Bypass mode is selected, the PLL will be off, and outputs will be running.
Power Connections
Pin Number
VDD
2
7
11,20
16
GND
5
6
10,21
15
Description
Input receiver analog
Digital Power
DIF outputs
PLL Analog
Note: epad on this device is not electrically connected to the die.
It should be connected to ground for best thermal performance.
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
2 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
2
REVISION D 04/22/15