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M1010-01 Datasheet, PDF (7/8 Pages) Integrated Circuit Systems – VCSO BASED CLOCK JITTER ATTENUATOR
Integrated
Circuit
Systems, Inc.
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%T,TAA==-400oCoCtoto++7805oCoC(c(oinmdmusetrricaial)l), FVCSO = FOUT = 150-175MHz, Outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Min Typ Max Unit Conditions
FIN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
18.75
175 MHz
50 MHz
FOUT Output Frequency
FOUT, nFOUT
150
175 MHz
APR VCSO Pull-Range
Commercial
Industrial
±120 ±200
ppm
±50 ±150
ppm
PLL Loop
Constants 1
KVCO VCO Gain
RIN
Internal Loop Resistor
BWVCSO VCSO Bandwidth
200
2050
700
kHz/V
kΩ
kHz
Φn
Phase Noise
and Jitter
J(t)
odc
tR
Single Side Band
Phase Noise
@155.52MHz
Jitter (rms)
@155.52MHz
Output Duty Cycle 2
Output Rise Time 2
for FOUT, nFOUT
1kHz Offset
10kHz Offset
100kHz Offset
12kHz to 20MHz
50kHz to 80MHz
-72
-94
-123
0.5
0.5
45
50
325 450
dBc/Hz Fin=19.44_MHz
dBc/Hz Mfin=8,
dBc/Hz M=x, R=x
ps
ps
55 %
500 ps 20% to 80%
tF
Output Fall Time 2
for FOUT, nFOUT
325 450
500 ps
20% to 80%
Table 9: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 5, Example Loop Filter Component Values for M1010-01-155.5200 on pg. 4.
Note 2: See Parameter Measurement Information on pg. 7.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
20%
Clock Output
80%
tR
80%
VP-P
20%
tF
Figure 5: Output Rise and Fall Time
FOUT
odc =
tPW
tPERIOD
tPW
(Output Pulse Width)
tPERIOD
Figure 6: Output Duty Cycle
M1010-01 Datasheet Rev 0.4
7 of 8
Revised 29Sep2003
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