M1010-01 Datasheet, PDF (3/8 Pages) Integrated Circuit Systems – VCSO BASED CLOCK JITTER ATTENUATOR

Integrated
Circuit
Systems, Inc.
M1010-01
VCSO BASED CLOCK JITTER ATTENUATOR
Preliminary Information
PLL DIVIDER LOOK-UP TABLES
Mfin (Frequency Input) Divider Look-Up Table (LUT)
The FIN_SEL1:0 pins select the feedback divider value
(“Mfin”).
FIN_SEL1:0
M1010-01-155.5200
Mfin Value _{Sample Ref. Freq. (MHz)} 1
00
8
19.44
01
10
11
2
77.76
1
155.52
x
Test mode. Do not use.
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
Note 1: Example with M1010-01-155.5200.
SEL2:0 Look-up Table (LUT)
The SEL2:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance.
SEL2:0 M
0 0 0 236
0 0 1 79
0 1 0 14
0 1 1 239
100 1
101 2
110 4
111 8
R
Description
236
79
14
239 _{Various divider values to adjust bandwidth}
1 and jitter tolerance
2
4
8
Table 4: SEL2:0 Look-up Table (LUT)
FUNCTIONAL DESCRIPTION
The M1010-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
A configurable frequency divider (labeled “Mfin Divider”)
provides the division options to accomodate various
reference clock frequencies.
In addition, configurable feedback and reference
dividers (the “M Divider” and “R Divider”) provide divider
value options to enable adjustment of loop bandwidth
and jitter tolerance.
For example, the M1010-01-155.5200 (see “Ordering
Information” on pg. 8) has a 155.52MHz VCSO
frequency:
The Mfin feedback divider allows an input frequency to
be the VCSO output frequency divided by 1, 2, or 8.
Therefore, for the base input frequency of 155.52MHz,
the actual input reference clock frequencies can be:
155.52, 77.76, and 19.44MHz. (See Table 3 on pg. 3.)
The PLL
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The “Mfin Divider” and “M Divider” divide the VCSO
frequency, feeding the result into the phase detector.
The selected input reference clock is divided by the “R
Divider”. The result is fed into the other input of the
phase detector.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output’s frequency and phase to those
of the input reference clock.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Relationship Among Frequencies and Dividers
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the M divider, the R divider,
and the input reference frequency (Fin) is:
Fvcso
=
Fin
×
Mfin
×
-^M--
R
Clock Output
The M1010-01 provides one differential LVPECL output
pair FOUT. PECL and LVDS product options are
available; consult factory.
M1010-01 Datasheet Rev 0.4
3 of 8
Revised 29Sep2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel [phone]