ICS97ULPA877A Datasheet, PDF (7/15 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS97UL PA8 77A
Switching Characteristics¹
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
(MHz)
Output enable time
Output disable time
Period jitter
t_en
t_dis
t_{jit (per)}
OE to any output
OE to any output
160 to 410
160 to 270
271 to 410
Half-period jitter
t_jit(hper)
160 to 270
271 to 410
Input slew rate
SLr1(i)
Input Clock
Output Enable (OE), (OS)
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
t _{jit (per) +} t _{(Ø)dyn +} t _skew(o)
t_{(Ø)dyn +} t_skew(o)
Output to Output Skew
SLr1(o)
t_jit(cc+)
t_jit(cc-)
t_(Ø)dyn
t_SPO2
∑(su)
∑_{t (h)}
t_skew
160 to 410
160 to 270
271 to 410
271 to 410
160 to 270
271 to 410
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
MIN
-40
-30
-60
-50
1
0.5
1.5
0
0
-50
-20
-50
30.00
0.00
2.0
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
TYP
4.73
5.82
2.5
2.5
0
MAX
8
8
40
30
60
50
4
3
40
-40
50
20
50
80
60
40
30
33
-0.50
UNITS
ns
ns
ps
ps
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
kHz
%
MHz
1088B—01/18/06
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