ICS97ULPA877A Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

Integrated
Circuit
Systems, Inc.
ICS97UL PA8 77A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/
SSTUA32864/SSTUA32866/SSTUA32S868/
SSTUA32S865/SSTUA32S869
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
• OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
• CYCLE - CYCLE jitter 40ps
Block Diagram
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
52-Ball BGA
Top View
1
A CLKT1
B CLKC1
C CLKC2
D CLKT2
E CLK_INT
F CLK_INC
G AGND
H AVDD
J CLKT3
K CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
5
CLKT5
G ND
G ND
OS
VDDQ
OE
VDDQ
G ND
G ND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
OE
OS
AV_DD
Powerdown
Control and
Test Logic
LD* or OE
LD*, OS or OE
LD*
PLL bypass
CLK_INT
CLK_INC
10K-100k
PLL
GND
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
VDDQ 1
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
GND 10
FB_OUTT
FB_OUTC
40
31
ICS97ULPA877A
11
20
40-Pin MLF
30 _CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
21 OS
1088B—01/18/06