ICS97ULPA877A Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS97UL PA8 77A
Timing Requirements
T_A = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
Application Frequency
Range
freq_op
freq_App
1.8V+0.1V @ 25°C
1.8V+0.1V @ 25°C
95
410
160
410
UNITS
MHz
MHz
Input clock duty cycle
d_{t in}
40
60
%
CLK stabilization
T_STAB
15
µs
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t₍Æ ), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK may be left floating after they have been driven low for one
complete clock cycle.
1088B—01/18/06
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