ICS950104 Datasheet, PDF (7/19 Pages) Integrated Circuit Systems – Programmable System Clock Chip for PIII Processor

ICS950104
Advance Information
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
11
10
24
8
8, 10,
11
-
1, 2
PWD
DESCRIPTION
X FS3#
1 REF2
1 REF1
1 48MHz
1 REF0
1
REF(2:0) 1X, 2X
default = 1=1X
1 (Reserved)
1 CPUCLKT/C0
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
33
32
-
45
23
PWD
DESCRIPTION
X FS0#
X FS1#
X FS2#
1 SDRAM6
1 SDRAM7
1 (Reserved)
1 CPUCLK
1 24_48MHz
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
1 (Reserved)
-
1
24_48MHz
select: 0=48MHz, 1=24MHz
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
-
0 (Reserved)
-
0 (Reserved)
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Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
-
X (Reserved)
Bit 6 21
1 PCICLK5
Bit 5 20
1 PCICLK4
Bit 4 19
1 PCICLK3
Bit 3 16
Bit 2 15
1 PCICLK2
1 PCICLK1
Bit 1 14
Bit 0 13
1 PCICLK0
1 PCICLK_F
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
41
40
39
38
35
34
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 SDRAM0
1 SDRAM1
1 SDRAM2
1 SDRAM3
1 SDRAM4
1 SDRAM5
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
1 Reserved (Note)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
7