ICS950104 Datasheet, PDF (6/19 Pages) Integrated Circuit Systems – Programmable System Clock Chip for PIII Processor

ICS950104
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit7 Bit2 Bit6 Bit5 Bit4 CPU
SDRAM
PCI
SS
0 0000
66.6
100.0
33.3
0 to-0.5%
0 0001
100.0
100.0
33.3
0 to-0.5%
0 0 0 10
150.0
100.0
37.5
±0.25%
0 00 11
133.3
100.0
33.3
0 to-0.5%
0 0 100
66.8
133.6
33.4
0 to-0.5%
0 0 10 1
100.0
133.3
33.3
0 to-0.5%
0 0 1 10
100.0
150.0
37.5
±0.25%
0 0 111
133.3
133.3
33.3
0 to-0.5%
0 1000
66.8
66.8
33.4
±0.25%
0 100 1
97.0
97.0
32.3
0 to-0.5%
0 10 10
70.0
105.0
35.0
±0.25%
0 10 11
95.0
95.0
31.7
±0.25%
0 1100
95.0
126.7
31.7
±0.25%
0 110 1
112.0
112.0
37.3
±0.25%
0 1 1 10
97.0
129.3
32.3
0 to-0.5%
Bit 7, 2, ^{0 1 1 1 1}
96.2
Bit 6:4 _{1 0 0 0 0}
66.8
96.2
100.2
32.1
0 to-0.5%
33.4
±0.25%
1 000 1
100.2
100.2
33.4
±0.25%
1 0 0 10
166.0
110.7
27.7
±0.25%
1 00 11
100.2
133.6
33.4
±0.25%
1 0 100
75.0
100.0
37.5
±0.25%
1 0 10 1
83.3
125.0
31.3
±0.25%
1 0 1 10
105.0
140.0
35.0
±0.25%
1 0 111
133.6
133.6
33.4
±0.25%
1 1000
110.3
147.0
36.8
±0.25%
1 100 1
115.0
153.3
38.3
±0.25%
1 10 10
120.0
120.0
30.0
±0.25%
1 10 11
138.0
138.0
34.5
±0.25%
1 1100
140.0
140.0
35.0
±0.25%
1 110 1
145.0
145.0
36.3
±0.25%
1 1 1 10
147.5
147.5
36.9
±0.25%
1 1111
160.0
160.0
26.7
±0.25%
Bit 3
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 7, 2, 6:4
Bit 1
0 - Normal
1 - Spread Spectrum Enabled
Bit 0
0 - Running
1- Tristate all outputs
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I²C readback for Bits 7, 2, 6:4 indicate the revision code.
I²C is a trademark of Philips Corporation
PWD
00010
Note1
0
1
0
Third party brands and names are the property of their respective owners.
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