ICS950104 Datasheet, PDF (5/19 Pages) Integrated Circuit Systems – Programmable System Clock Chip for PIII Processor

ICS950104
Advance Information
Brief I²C registers description for ICS950104
Programmable System Frequency Generator
Register Name
Functionality & Frequency
Select Register
Output Control Registers
Byte
0
1-6
D es crip tion
Output frequency, hardware / I²C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
PWD Default
See individual
byte description
See individual
byte description
Vendor ID & Revision ID
R egis ters
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
Writing to this register will configure
8
byte count and how many byte will be
08H
read back. Do not write 00H to this byte.
Watchdog Timer
Count Register
Writing to this register will configure the
9
number of seconds for the watchdog
10H
timer to reset.
Watchdog Control Registers 10 Bit [6:0]
VCO Control Selection Bit 10 Bit [7]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
000,0000
0
VCO Frequency Control
R egis ters
11-12
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
R egis ters
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
R egis ters
15-16
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I²C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
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