ICS93738 Datasheet, PDF (7/8 Pages) Integrated Circuit Systems – DDR and SDRAM Buffer

ICS93738
General I²C serial interface information
The information in this section assumes familiarity with I²C programming.
For more information, contact ICS for an I²C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D5
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 7
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Write:
How to Read:
Controller (Host)
Start Bit
Address
D4(H)
Dummy Command Code
Dummy Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Stop Bit
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Controller (Host)
Start Bit
Address
D5(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
ICS (Slave/Receiver)
ACK
Byte Count
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Notes:
1. The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches
for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I²C interface, the protocol is set to use only "Block-Writes" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be
sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
0689A—01/09/03
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