ICS93738 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – DDR and SDRAM Buffer

Integrated
Circuit
Systems, Inc.
ICS93738
DDR and SDRAM Buffer
Recommended Application:
DDR & SDRAM fanout buffer, for VIA P4X/KT266/333
chipsets.
Product Description/Features:
• Low skew, fanout buffer
• 1 to 12 differential clock distribution
• I²C for functional and output control
• Feedback pin for input to output synchronization
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs
+ 2 DDR DIMMs
• Frequency supports up to 200MHz (DDR400)
• Supports Power Down Mode for power
mananagement
• CMOS level control signal input
Switching Characteristics:
• OUTPUT - OUTPUT skew: <100ps SDRAM
OUTPUT - OUTPUT skew: <150ps DDR
• Output Rise and Fall Time for DDR outputs: 600ps -
950ps
• DUTY CYCLE: 47% - 53% DDR
DUTY CYCLE: 45%- 55% SDRAM
Pin Configuration
FB_OUT
1
VDD3.3_2.5
2
GND
3
DDRT0_SDRAM0
4
DDRC0_SDRAM1
5
DDRT1_SDRAM2
6
DDRC1_SDRAM3
7
VDD3.3_2.5
8
GND
9
DDRT2_SDRAM4
10
DDRC2_SDRAM5
11
VDD3.3_2.5
12
BUF_IN
13
GND
14
DDRT3_SDRAM6
15
DDRC3_SDRAM7
16
VDD3.3_2.5
17
GND
18
DDRT4_SDRAM8
19
DDRC4_SDRAM9
20
DDRT5_SDRAM10
21
DDRC5_SDRAM11
22
VDD3.3_2.5
23
SDATA
24
48
SEL_DDR*
47
VDD2.5
46
GND
45
DDRT11
44
DDRC11
43
DDRT10
42
DDRC10
41
VDD2.5
40
GND
39
DDRT9
38
DDRC9
37
VDD2.5
36
PD#*
35
GND
34
DDRT8
33
DDRC8
32
VDD2.5
31
GND
30
DDRT7
29
DDRC7
28
DDRT6
27
DDRC6
26
GND
25
SCLK
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Block Diagram
BUF_IN
SCLK
SDATA
SEL_DDR*
PD#
Control
Logic
0689A—01/09/03
Functionality
FB_OUT
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
DDRT2_SDRAM4
DDRC2_SDRAM5
DDRT3_SDRAM6
DDRC3_SDRAM7
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
DDRT(11:6)
DDRC (11:6)
MODE
DDR
Mode
DDR/SD
Mode
PIN 48
VDD
3.3_2.5
PIN
4, 5, 6, 7, 10, 11, 15,
16, 19, 20, 21, 22
SEL_DDR=1
2.5V
These outputs will be
DDR outputs
SEL_DDR=0
3.3V
These outputs will be
standard SDRAM
outputs