ICS93738 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – DDR and SDRAM Buffer

ICS93738
Switching Characteristics
T_A = 0 - 85^oC
PARAMETER
SYMBOL
Operating Frequency
Input clock duty cycle
Output to output Skew¹
(DDR outputs)
Output to output Skew¹
(SDRAM outputs)
Duty Cycle^1,3
(DDR outputs)
Duty Cycle^1,3
(SDRAM outputs)
d_tin
T_skewDDR
T_skewSD
DC_DDR
DC_SD
Rise Time, Fall Time¹ (DDR
outputs)
t_rd, t_fd
Rise Time, Fall Time¹
(SDRAM outputs)
t_rs, t_fs
SDRAM Buffer LH
Propagation Delay^1,2
t_PLH
SDRAM Buffer HL
Propagation Delay^1,2
t_PHL
CONDITIONS
MIN
66
40
V_T = 50%, Not including FB_OUT to outputs
V_T = 1.5V
V_T = 50%, 66 MHz to 100 MHz , w/loads 48
V_T = 50%, 101 MHz to 167 MHz, w/loads 47
V_T = 1.5V, w/loads
45
Single-ended 20 - 80 %
600
133 MHz, Load = 120Ω / 12 pF
Single-ended V_OL = 0.4V, V_OH = 2.4V
0.5
133 MHz, Load = 12 pF
Input edge greater than 1V/ns
Input edge greater than 1V/ns
TYP MAX
133 200
50 60
80 150
70 100
49 52
50 53
50 55
800 950
1.5 1.7
2
2.5
1.9 2.5
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting output.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formula: duty cycle = t2 / t1, where the cycle time (t1) decreases as the frequency increases.
UNITS
MHz
%
ps
ps
%
%
ps
ns
ns
ns
Switching Waveforms
Duty Cycle Timing
t₁
t₂
1.5V
1.5V
1.5V
SDRAM Buffer LH and HL Propagation Delay
INPUT
1.5V
1.5V
OUTPUT
t₆
0689A—01/09/03
1.5V
1.5V
t₇
6