ICS8705 Datasheet, PDF (7/17 Pages) Integrated Circuit Systems – ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8705
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
15.625
250
tp_LH
Propagation Delay,
CLK0
Low-to-High; NOTE 1 _{CLK1, nCLK1}
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
PLL_SEL = 0V,
f ≤ 250MHz, Qx ÷ 2
5
5
7
7.3
CLK0
PLL_SEL = 2.5V,
fREF ≤ 200MHz, Qx ÷ 1
-250
25
200
PLL_SEL = 2.5V,
t(Ø)
Static Phase Offset;
NOTE 2, 4
CLK1, nCLK1
fREF = 133MHz, Qx ÷ 1
PLL_SEL = 2.5V,
fREF = 200MHz, Qx ÷ 1
-50
-100
100
+100
250
300
CLK0
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
-150
-25
100
CLK1, nCLK1
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
0
150
300
tsk(o)
Output Skew;
NOTE 3, 4
CLK0
CLK1, nCLK1
PLL_SEL = 0V
PLL_SEL = 0V
65
55
tjit(cc) Cycle-to-Cycle Jitter; NOTE 4
f_OUT > 40MHz
45
tjit(θ) Phase Jitter; NOTE 4, 5
PLL_SEL = 2.5V,
fREF = 66MHz, Qx * 2
±50
t_L
t_R / t_F
PLL Lock Time
Output Rise/Fall Time
1
400
950
43
57
odc
Output Duty Cycle
PLL x 4 mode, fin = 45MHz,
fOUT = 180MHz
45
55
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V_DDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Phase jitter is dependent on the input source used.
Units
MHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
mS
ps
%
%
8705BY
www.icst.com/products/hiperclocks.html
7
REV. G JUNE 16, 2004