ICS8705 Datasheet, PDF (2/17 Pages) Integrated Circuit Systems – ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8705
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 11
3
SEL0, SEL1,
SEL2
CLK0
Input
Input
Pulldown
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
4
nc
No connect.
5
CLK1
Input Pulldown Non-inverting differential clock input.
6
nCLK1
Input Pullup Inverting differential clock input.
7
8
9, 32
10
12, 16, 20,
24, 28
13, 15, 17,
19, 21, 23,
25, 27
CLK_SEL
MR
V_DD
FB_IN
Input
Input
Power
Input
Pulldown
Pulldown
Pulldown
Clock select input. When HIGH, selects differential CLK1, nCLK1.
When LOW, selects LVCMOS CLK0.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
Core supply pins.
LVCMOS/LVTTL feedback input to phase detector for regenerating
clocks with "zero delay". Connect to one of the outputs.
LVCMOS/LVTTL interface levels.
V_DDO
Q0, Q1, Q2,
Q3, Q4, Q5,
Q6, Q7
Power
Output
Output supply pins.
Clock output. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
14, 18, 22, 26
GND
Power
Power supply ground.
29
SEL3
Input
Pulldown
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
30
V_DDA
Power
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
31
PLL_SEL Input Pullup When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
C_PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
V_DD, V_DDO, V_DDA = 3.465V
Minimum
Typical
4
51
51
23
7
Maximum
Units
pF
KΩ
KΩ
pF
Ω
8705BY
www.icst.com/products/hiperclocks.html
2
REV. G JUNE 16, 2004