ICS8705 Datasheet, PDF (1/17 Pages) Integrated Circuit Systems – ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
ICS8705
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8705 is a highly versatile 1:8 Differen-
ICS
tial-to-LVCMOS/LVTTL Clock Generator and a
HiPerClockS™ _{member of the HiPerClockS™family of High Per-}
formance Clock Solutions from ICS.The ICS8705
has two selectable clock inputs. The CLK1,
nCLK1 pair can accept most standard differential input lev-
els. The single ended CLK0 input accepts LVCMOS or LVTTL
input levels.The ICS8705 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to
250MHz. The reference divider, feedback divider and output
divider are each programmable, thereby allowing for the fol-
lowing output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2,
1:4, 1:8. The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks.
The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
FEATURES
• 8 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PLL_SEL
CLK0
÷2, ÷4, ÷8, ÷16,
÷32, ÷64, ÷128
0
CLK1
nCLK1
CLK_SEL
FB_IN
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
SEL1
SEL2
SEL3
MR
8705BY
PIN ASSIGNMENT
Q0
0
Q1
1
Q2
32 31 30 29 28 27 26 25
SEL0 1
Q3
SEL1 2
24 VDDO
23 Q5
Q4
CLK0 3
22 GND
Q5
nc 4
CLK1 5
ICS8705
21 Q4
20 VDDO
nCLK1 6
Q6
CLK_SEL 7
19 Q3
18 GND
Q7
MR 8
17 Q2
9 10 11 12 13 14 15 16
www.icst.com/products/hiperclocks.html
1
32-Lead LQFP
7mm x 7mm x 1.4 mm
Y Package
Top View
REV. G JUNE 16, 2004