ICS844252-04 Datasheet, PDF (7/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844252-04
FEMTOCLOCKS™ CRYSTAL-TO-
LVDS CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844252-04 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. V_DD, V_DDA,
and V_DDO should be individually connected to the power
supply plane through vias, and bypass capacitors should
be used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V_CCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
V_DD
.01μF 10Ω
V_DDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844252-04 has been characterized with 18pF paral-
lel resonant crystals. The capacitor values, C1 and C2, shown
in Figure 2 below were determined using a 25MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
X1
18pF Parallel Crystal
XTAL_OUT
C1
22p
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
844252AG-04
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7
REV. A JANUARY 26, 2006