ICS844071I Datasheet, PDF (7/10 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844071I
FEMTOCLOCKS™CRYSTAL-TO- LVDS
CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS844071I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for dif-
ferent board layouts.
X1
18pF Parallel Crystal
XTAL_OUT
C1
22p
XTAL_IN
C2
33p
Figure 2. CRYSTAL INPUt INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
VDD
LVDS_Driv er
R1
100
100 Ohm Differential Transmission Line
2.5V or 3.3V
+
-
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844071AGI
www.icst.com/products/hiperclocks.html
7
REV. A JULY 13, 2005