ICS844071I Datasheet, PDF (6/10 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO- LVDS CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844071I
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844071I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_DD and V_DDA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V_DDA pin.
V_DD
V
DDA
3.3V or 2.5V
.01μF 10 Ω
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the TEST_CLK to ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resister can be tied from CLK
to ground.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
LVDS OUTPUT
All unused LVDS outputs should be terminated with 100Ω resister
between the differential pair.
LVDS – Like OUTPUT
All unused LVDS outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
HCSL OUTPUT
All unused HCSL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resister can be used.
SSTL OUTPUT
All unused SSTL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
844071AGI
www.icst.com/products/hiperclocks.html
6
REV. A JULY 13, 2005