ICS348-22 Datasheet, PDF (7/8 Pages) Integrated Circuit Systems – Quad PLL Field Programmable VersaClock Synthesizer

PRELIMINARY INFORMATION
ICS348-22
Quad PLL Field Programmable VersaClock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C
Parameter
Symbol
Conditions
Min.
Input Frequency
Output Frequency
F_IN Fundamental Crystal
VDD=3.3 V
0.25
Output Rise Time
Output Fall Time
Duty Cycle
t_OR 20% to 80%, Note 1
t_OF 80% to 20%, Note 1
Note 2
40
Power-up time
PLL lock-time from
power-up, Note 3
PDTS goes high until
stable CLK output, Note 3
One Sigma Clock Period Jitter
Configuration Dependent
Maximum Absolute Jitter
t_ja
Deviation from Mean.
Configuration Dependent
Pin-to-Pin Skew
Low Skew Outputs
-250
Typ.
25
1
1
49-51
3
0.2
50
+200
Max. Units
MHz
189 MHz
ns
ns
60
%
10 ms
2
ms
ps
ps
250 ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS
transition high on select address change.
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θ_JA Still air
θ_JA 1 m/s air flow
θ_JA 3 m/s air flow
Thermal Resistance Junction to Case θ_JC
Min.
Typ.
135
93
78
60
Max.
Units
°C/W
°C/W
°C/W
°C/W
MDS 348-22 A
7
Revision 120704
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