ICS348-22 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Quad PLL Field Programmable VersaClock Synthesizer

PRELIMINARY INFORMATION
ICS348-22
Quad PLL Field Programmable VersaClock Synthesizer
Pin Assignment
X1 1
S0 2
S1 3
CLK9 4
VDD 5
GND 6
CLK1 7
CLK2 8
CLK3 9
CLK4 10
20 X2
19 VDD
18 PDTS
17 S2
16 VDD
15 GND
14 CLK5
13 CLK6
12 CLK7
11 CLK8
20-pin (150 mil) SSOP (QSOP)
Output Configuration Table
S2 S1 S0
Outputs
0 0 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
0 0 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
0 1 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
0 1 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1 0 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1 0 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1 1 0 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=187 MHz, CLK8=189 MHz, CLK9=127 MHz
1 1 1 CLK1=CLK2=CLK3=CLK4=CLK5=127 MHz, CLK6=CLK7=OFF, CLK8=189 MHz, CLK9=127 MHz
MDS 348-22 A
2
Revision 120704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com