ICS93718 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – DDR and SDRAM Buffer

ICS9371 8
Switching Characteristics
DDR_Mode (SEL_DDR = 1), VDD = 2.5±5%
PARAMETER
Operating Frequency
SYMBOL
CONDITION
MIN TYP MAX UNITS
66 133 200 MHz
Input clock duty cycle
d_tin
40
50
60
%
Output to Output Skew
Duty cycle
T_skew Output crossover skew DDR[0:11]
D_C2
66MHz to 100MHz, w/loads
101MHz to 167MHz, w/loads
48
47
80 100 ps
49
52
%
50
53
%
Rise Time, Fall Time (DDR
Measured between 20% and 80%
Outputs)
trd, tfd _{output, w/loads}
500 600 700 ps
Switching Characteristics
SD_Mode (SEL_DDR = 0), VDD = 3.3±5%
PARAMETER
Operating Frequency
Input clock duty cycle
Output to Output Skew
Duty cycle
Rise Time, Fall Time
(SDRAM Outputs)
SDRAM Buffer LH Prop.
Delay¹
SYMBOL
CONDITION
d_tin
T_skew
D_C2
trs, tfs
V_T = 1.50V
66MHz to 200MHz
V_OL = 0.4V, V_OH = 2.4V, w/loads
t^PLH Input edge greater than 1V/ns
MIN TYP
66 133
40 50
150
54
0.5 1.5
2
SDRAM Bufer HL Prop.
Delay¹
t^PHL Input edge greater than 1V/ns
1.9
Notes:
1. Refers to transition on non-inverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=t2/t1, were the cycle (t1) decreases
as the frequency goes up.
Switching Waveforms
Duty Cycle Timing
t₁
t₂
1.5V
1.5V
1.5V
MAX
200
60
UNITS
MHz
%
ps
%
1.7 ns
2.5 ns
2.5 ns
SDRAM Buffer LH and HL Propagation Delay
INPUT
1.5V
1.5V
OUTPUT
t₆
0434D—10/10/03
1.5V
1.5V
t₇
6