ICS93718 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – DDR and SDRAM Buffer

ICS9371 8
Pin Descriptions
PIN NUMBER
PIN NAME
1
FB_OUT
2, 8, 12, 17, 23, VDD3.3_2.5
3, 9, 14, 18, 26,
31, 35, 40, 46
45, 43, 39,
34, 30, 28,
GND
DDRT (11:6)
44, 42, 38,
33, 29, 27,
DDRC (11:6)
21, 19, 15, 10, 6, 4
DDRT (5:0)
SDRAM (10, 8, 6, 4, 2, 0)
DDRC (5:0)
22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3,
1,)
13
BUF_IN
24
SDATA
25
SCLK
32, 37, 41, 47 VDD2.5
36
PD#
48
SEL_DDR
TYPE
DESCRIPTION
OUT Feedback output, dedicated for external feedback
PWR
2.5V or 3.3V voltage supply to pins
4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22
PWR Ground
OUT "True" Clock of differential pair outputs.
OUT "Complementory" clocks of differential pair outputs.
OUT
"True" Clock of differential pair outputs, or 3.3V SDRAM
clock outputs depending on SEL_DDR input
OUT
"Complementory" clocks of differential pair outputs, or 3.3V
SDRAM clock outputs depending on SEL_DDR input
IN Single ended buffer input
I/O Data pin for I²C circuitry 5V tolerant
IN Clock input of I²C input, 5V tolerant input
PWR
IN
IN
2.5V voltage supply
Asynchronous active low input pin used to power down the
device into a low power state. The internal clocks are
disabled. The latency of the power down will not be greater
than 3ms.
Select input for DDR mode or DDR/SD mode
0=DDR/SD mode 1=DDR mode
0434D—10/10/03
2