ICS93718 Datasheet, PDF (3/8 Pages) Integrated Circuit Systems – DDR and SDRAM Buffer

ICS9371 8
Byte 6: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
48
-
-
-
45, 44
43, 42
39, 38
34, 33
PWD
DESCRIPTION
1 SEL_DDR (Read back only)
1 (Reserved)
1 (Reserved)
1 (Reserved)
1 DDRT11, DDRC11
1 DDRT10, DDRC10
1 DDRT9, DDRC9
1 DDRT8, DDRC8
Byte 7: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
30, 29
28, 27
21, 22
19, 20
15, 16
10, 11
6, 7
4, 5
PWD
DESCRIPTION
1 DDRT7, DDRC7
1 DDRT6, DDRC6
1
DDRT5, SDRAM10
DDRC5_SDRAM11
1
DDRT4_SDRAM8
DDRC4_SDRAM9
1
DDRT3_SDRAM6
DDRC3_SDRAM7
1
DDRT2_SDRAM4
DDRC2_SDRAM5
1
DDRT1_SDRAM2
DDRC1_SDRAM3
1
DDRT0_SDRAM1
DDRC0_SDRAM0
0434D—10/10/03
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