ICS93701 Datasheet, PDF (6/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS9370 1
Switching Characteristics
PARAMETER
SYMBOL
Low-to high level
propagation delay time
t_PLH1
High-to low level
propagation delay time
t_PHL1
Output enable time
t_EN
Output disable time
tdis
Period Jitter
Half-period jitter
t(jit_hper)
Cycle to Cycle Jitter1
Phase error
Output to Output Skew
Pulse skew
T_cyc-T_cyc
t_{(phase error)}
T_skew
T_skewp
Duty cycle
DC²
Slew Rate
t_SLEW
CONDITION
CLK_IN to any output
CLK_IN to any output
PD# to any output
PD# to any output
100/133/166MHz
100/133/166MHz
100/133/166MHz
100/133/166Mhz
66MHz to 100MHz
101MHz to 133MHz
135MHz to 167MHz
Load = 120Ω/14pF
MIN
-40
-120
-150
49.5
48.5
48.5
1
TYP
3.5
3.5
3
3
±25
±50
30
-100
60
60
50
49
49
1.9
Notes:
1. Refers to transition on noninverting outputs in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error increases at
high frequencies. This is due to the formula: duty cycle=t_wH/t_c, where the cycle (t_c)
decreases as the frequency goes up.
MAX
40
100
65
150
100
100
50.5
50
50
2
UNITS
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
%
%
%
ps
0417B—10/29/02
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