ICS93701 Datasheet, PDF (1/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

Integrated
Circuit
Systems, Inc.
ICS9370 1
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• DUTY CYCLE: 49.5% - 50.5%
• Slew rate: 1V/ns - 2V/ns
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
SCLK
CLK_INT
CLK_INC
VDDI²C
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
48
GND
2
47
CLKC5
3
46
CLKT5
4
45
VDD
5
44
CLKT6
6
43
CLKC6
7
42
GND
8
41
GND
9
40
CLKC7
10
39
CLKT7
11
38
VDD
12
37
SDATA
13
36
FB_INC
14
35
FB_INT
15
34
VDD
16
33
FB_OUTT
17
32
FB_OUTC
18
31
GND
19
30
CLKC8
20
29
CLKT8
21
28
VDD
22
27
CLKT9
23
26
CLKC9
24
25
GND
48-Pin TSSOP
Block Diagram
SCLK
SDATA
Control
Logic
FB_INT
FB_INC
CLK_INC
PLL
CLK_INT
0417B—10/29/02
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
Functionality
AVDD
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
INPUTS
CLK_INT CLK_INC
L
H
H
L
<20MHz)⁽¹⁾
OUTPUTS
CLKT CLKC FB_OUTT
LH
L
HL
H
Z
Z
Z
FB_OUTC
H
L
Z
PLL State
on
on
off