ICS93701 Datasheet, PDF (3/9 Pages) Integrated Circuit Systems – DDR Phase Lock Loop Clock Driver

ICS9370 1
Byte 0: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
3, 2
5, 6
10, 9
20, 19
22, 23
46, 47
44, 43
39, 40
PWD
DESCRIPTION
1 CLKT0, CLKC0
1 CLKT1, CLKC1
1 CLKT2, CLKC2
1 CLKT3, CLKC3
1 CLKT4, CLKC4
1 CLKT5, CLKC5
1 CLKT6, CLKC6
1 CLKT7, CLKC7
Byte 2: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Byte 4: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Byte 1: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
29, 30
27, 26
-
-
-
-
-
-
PWD
DESCRIPTION
1 CLKT8, CLKC8
1 CLKT9, CLKC9
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Byte 3: Reserved
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Byte 5: Reserved
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
0417B—10/29/02
3