ICS9250-10 Datasheet, PDF (6/16 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9250 - 10
Preliminary Product Preview
Byte 5:ICS Reserved Functionality and frequency select register (Default=0)
Bit
Bit7
Bit6
Bit5
Bit
(4,3,0)
Bit2
Bit1
Desctiption
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
ICS RESERVED BIT (Needs to be 0 clock to operate normal)
FS0
(HW)
Bit (4,3,0)
SEL3 SEL2
(Bit4) (Bit3)
CPUCLK SDRAM 3V66 PCICLK
SEL1
MHz
MHz MHz MHz
(Bit0)
0
0
0
0
66.67
100 66.67 33.33
0
0
0
1
70.67
106 70.67 35.33
0
0
1
0
74.66
112 74.67 37.33
0
0
1
1
82.66
124 82.66 41.33
0
1
0
0
63.5
95.25 63.5 31.75
0
1
0
1
68.67
103 68.67 34.33
0
1
1
0
72.67
109 72.67 36.33
0
1
1
1
88.66
133 88.66 44.33
1
0
0
0
100
100 66.67 33.33
1
0
0
1
106
106 70.67 35.33
1
0
1
0
112
112 74.67 37.33
1
0
1
1
124
124 82.66 41.33
1
1
0
0
95.25 95.25 63.5 31.75
1
1
0
1
103
103 68.67 34.33
1
1
1
0
109
109 72.67 36.33
1
1
1
1
133
133 88.66 44.33
Not used (Needs to be 1 for normal clock operation)
Not used (Needs to be 1 for normal clock operation)
PWD
0
0
0
XXXX
Note 1
1
1
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
6