ICS9250-10 Datasheet, PDF (4/16 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9250 - 10
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
810E
Condition
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
Powerdown Mode
(PWRDWN# = 0
10mA
10mA
Full Active 66MHz
SEL1, 0 = 10
70mA
280mA
Full Active 100MHz
SEL1, 0 = 11
100mA
280mA
4