ICS9250-10 Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Frequency Timing Generator for Pentium II Systems

ICS9250 - 10
Preliminary Product Preview
Pin Descriptions
PIN NUMBER PIN NAME
FREQ_APIC
1
REF0
3
X1
4
X2
5, 6, 14, 17, 23,
24, 35, 41, 47
GND (0:5)
8, 7
3V66 [1:0]
2, 9, 10, 21,
22, 27, 33, 38, 44
20,19,18,16,
15,13,12,11
VDD (0:5)
PCICLK[7:0]
25, 26
48MHz (0:1)
28, 29
FS (0:1)
30
SDATA
31
SCLK
32
PD#
36, 37, 39, 40, 42,
43, 45, 46
SDRAM [7:0]
34
SDRAM_F
56,48
GNDL [1:0]
49,50,52
CPUCLK [2:0]
51, 53
54, 55
VDDL (0:1)
IOAPIC [1:0]
TYPE
IN
OUT
IN
OUT
DESCRIPTION
Latched input at Power On. this determines the IOAPIC frequency.
When a "0" is latched, IOAPIC Freq=16.67MHz
When "1" is latched, IOAPIC Freq=33.3MHz
This pin has a 60K internal pull-up.
3.3V, 14.318MHz reference clock output.
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
PWR Ground pins for 3.3V supply
OUT 3.3V Fixed 66MHz clock outputs for HUB
PWR 3.3V power supply
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
OUT
IN
IN
3.3V Fixed 48MHz clock outputs for USB
Function Select pins. Determines CPU frequency, all output
functionality. Please refer to Functionality table on page 3.
Data input for I²C serial input.
IN
IN
OUT
OUT
Clock input of I²C input
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down
will not be greater than 3ms.
3.3V output running 100MHz. All SDRAM outputs can be turned
off through I²C
3.3V free running 100MHz SDRAM not affected by I²C
PWR
OUT
PWR
Ground for 2.5V power supply for CPU & APIC
2.5V Host bus clock output. 66MHz or 100MHz depending on FS
(0:1) pins Refer page 3.
2.5V power suypply for CPU & IOAPIC
OUT 2.5V clock outputs running at 16.67MHz or 33.3MHz.
2