ICS9177 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – High Frequency System Clock Generator

ICS9177
Table 6: AC Specification type Out B.ttl Pins (50 MHz)
PARAMETER
SYMBOL TEST CONDITIONS
MIN
Output High Voltage
Voh
2.4
Output Low Voltage
Vol
0
Output High Current
Ioh
16
Output Low Current
Iol
Rise Time 10-90%
tr
1
Fall Time 10-90%
tf
1
Pin skew to other OutB.ttl
signals ¹
tsk
Duty cycle at 1.5V
dcyc
45
Delay from OutA.pecl signals ²
tdly
Skew associated with above
delay ³
tdlyskw
TYP
MAX
3.2
5
0.3
0.8
24
2
3
2
3
250
500
55
.2
.5
±0.5
UNITS
volts
volts
mA
mA
ns
ns
ps
%
ns
ns
Test Load Conditions: 500Ω, 15 pF.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from
the OutA.pecl signal at the signal swing mid-point to max output of the OutB.ttl signal’s rising edge
Table 7: AC Specification type Out C.ttl Pins (25 MHz)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
Pin skew to other OutC.ttl
signals ¹
Duty cycle at 1.5V
Spread to OutB.ttl signals ²
SYMBOL TEST CONDITIONS
MIN
Voh
2.4
Vol
0
Ioh
16
Iol
tr
1
tf
1
tsk
dcyc
45
tspb
TYP
MAX
3.2
5
0.3
0.8
24
2
3
2
3
250
500
55
500
UNITS
volts
volts
mA
mA
ns
ns
ps
%
ps
Test Load Conditions: 500Ω, 15 pF.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Spread is the absolute difference between the rising edge of any OutC.ttl signal and the rising edge of any OutB.ttl
signal
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