ICS9159-14 Datasheet, PDF (6/7 Pages) Integrated Circuit Systems – Frequency Generator and Integrated Buffer for PENTIUM™

ICS9159-14
Electrical Characteristics at 5.5V
V_DD = 4.5 – 5.5 V, T_A = 0 – 70° C
PARAMETER
Rise Time¹
Fall Time¹
Rise Time¹
Fall Time¹
Duty Cycle¹
Duty Cycle¹
Jitter, One Sigma¹
Jitter, Absolute¹
Jitter, One Sigma¹
Jitter, Absolute¹
Input Frequency¹
Logic Input Capacitance¹
Crystal OscillatorCapacitance¹
Power-on Time¹
Frequency Settling Time¹
Clock Skew Window¹
Clock Skew Window¹
Clock Skew Window¹
AC Characteristics
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
Tr1
20pF load, 0.8 to 2.0V CPU & BUS
-
0.55 0.95 ns
Tf1
20pF load, 2.0 to 0.8V CPU & BUS
-
0.52 0.90 ns
Tr2
20pF load, 20% to 80%CPU & BUS
-
1.2
2.1
ns
Tf2
20pF load, 80% to 20% CPU & BUS
-
1.1 2.0
ns
Dt1
Dt2
Tj1s1
Tjab1
Tj1s2
20pF load @ V_OUT=1.4V
20pF load @ V_OUT=50%
W ^{CPU & BUS Clocks; Load=20pF,}
RS=33 FOUT>25 MHz
W ^{CPU & BUS Clocks; Load=20pF,}
RS=33 FOUT>25 MHz
REF CLKs; Load=20pF RS=33W
52
57
62
%
45
50
55
%
-
50 150 ps
-250
-
250 ps
-
1
3
%
Tjab2 REF CLKs; Load=20pF RS=33W
-5
2
5
%
Fi
12.0 14.318 16.0 MHz
CIN
Logic input pins
-
5
-
pF
CINX X1, X2 pins
-
ton
From VDD=1.6V to 1 st crossing of 66.5
MHz VDD supply ramp < 40ms
-
ts
From 1st crossing of acquisition to < 1%
settling
-
Tsk1 CPU to CPU; Load=20pF; @1.4V
-
18
-
pF
2.5 4.5 ms
2.0 4.0 ms
150 250 ps
Tsk2 BUS to BUS; Load=20pF; @1.4V
-
300 500 ps
Tsk3
CPU & BUS; Load=20pF; @1.4V
1
2.6
5
ns
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
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