ICS9112-06 Datasheet, PDF (6/8 Pages) Integrated Circuit Systems – Low Skew Output Buffer

ICS9112-06/07
Switching Characteristics (5.0V Continued)
PARAMETER
Output period
SYMBOL
CONDITION
t1
With CL=30pF
Output period
Duty Cycle¹
Rise Time¹
Rise Time¹
Fall Time¹
Fall Time¹
Delay, REF Rising
Edge to CLKOUT
Rising Edge^{1, 2}
Output to Output
Skew¹
Device to Device
Skew¹
Cycle to Cycle Jitter¹
PLL Lock Time¹
Jitter; Absolute Jitter¹
Jitter; 1 - Sigma¹
t1
With CL=20pF
Dt1
Measured at 1.4V; CL=30pF
tr1
Measured between 0.8V and 2.0V:
CL=30pF
tr2
Measured between 0.8V and 2.0V:
CL=20pF
tf1
Measured between 2.0V and 0.8V;
CL=30pF
tf2
Measured between 2.0V and 0.8V;
CL=20pF
Dr1
Measured at VDD/2
Tskew All outputs equally loaded, CL=20pF
Tdsk-Tdsk
Tcyc-Tcyc
tLOCK
Tjabs
Tj1s
Measured at VDD/2 on the CLKOUT
pins of devices
Measured at 66.66 MHz, loaded
outputs
Stable power supply, valid clock
presented on REF pin
@ 10,000 cycles
CL=30pF F=20 - 50MHz
@ 10,000 cycles
CL=30pF F=20 - 50MHz
MIN
60.00
(30)
60.00
(30)
40.0
-400
-200
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of VDD/2
3. All parameters expected with loaded outputs
TYP
MAX
UNITS
20.00
(50)
16.11
(90)
ns
(MHz)
ns
(MHz)
49.1
60
%
1.5
2.3
ns
0.7
1.8
ns
1.2
2.3
ns
0.9
1.8
ns
0
+400
ps
80
250
ps
0
700
ps
300
1.5
ms
80
100
ps
14
30
ps
PB