ICS9112-06 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – Low Skew Output Buffer

Integrated
Circuit
Systems, Inc.
ICS9112-06/07
Low Skew Output Buffer
General Description
The ICS9112 is a high performance, low skew, low jitter clock
driver. It uses a phase lock loop (PLL) technology to align, in
both phase and frequency, the REF input with the CLKOUT
signal. It is designed to distribute high speed clocks in PC
systems operating at speeds from 25 to
75 MHz (30 to 90mHz for 5V operation).
ICS9112 is a zero delay buffer that provides synchronization
between the input and output. The synchronization is
established via CLKOUT feed back to the input of the PLL.
Since the skew between the input and output is less than +/-
350 pS, the part acts as a zero delay buffer.
Features
• Zero input - output delay
• Frequency range 25 - 75 MHz (3.3V), 30-90MHz (5.0V)
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 or 16 pin versions, 150 mil SOIC packages
• 3.3V ±10%, 5.0V±10% operation
Pin Configuration
The ICS9112 comes in with two different options; dash 06
and dash 07. The dash 07 is available in a 16 pin 150 mil SOIC
package. It has two banks of four outputs controlled by two
address lines. Depending on the selected address line, bank B
or both banks can be put in a tri-state mode. In this mode, the
PLL is still running and only the output buffers are put in a
high impedance mode. The test mode shuts off the PLL and
connects the input directly to the output buffers (see table
below for functionality).
The dash 06 is an eight pin 150 mil SOIC package. It has five
output clocks. In the absence of REF input, both ICS9112-06
and -07 will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low. Power
down mode provides the lowest power consumption for a
standby condition.
16 pin SOIC
Block Diagram
9112-06 9112-07 Rev H 1/22/99
8 pin SOIC
Functionality (-07)
FS2
FS1
CLKA
(1, 4)
CLKB
(1, 4)
CLKOUT
Output
Source
0 0 Tristate Tristate Driven PLL
0 1 Driven Tristate Driven PLL
1
0
Test Test
Mode Mode
Test
Mode
REF
1 1 Driven Driven Driven PLL
PLL
Shutdown
N
N
Y
N
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all device
data to verify that any information being relied upon by the customer is current and accurate.