ICS8752 Datasheet, PDF (6/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE
6A.
PLL
INPUT
REFERENCE
CHARACTERISTICS,
V
DD
=
V
DDA
=
V=
DDO
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol
f_REF
Parameter
Input Reference Frequency
NOTE: Input reference frequency is limited by
the divider selection and the VCO lock range.
Test Conditions
Minimum Typical Maximum Units
20
240
MHz
TABLE 7A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
÷2
110
240
MHz
÷4
55
120
MHz
f_OUT
Output Frequency (PLL Mode)
÷6
36.67
÷8
27.5
80
MHz
60
MHz
÷12
18.33
40
MHz
f_VCO
PLL VCO Lock Range
t(Ø)
Static Phase Offset; NOTE 1
fVCO = 400MHz,
Feedback ÷ 8
220
480
-30
70
170
tsk(b) Bank Skew; NOTE 2, 4
Measured on rising edge
at V_DDO/2
55
tsk(o) Output Skew; NOTE 3, 4
Measured on rising edge
at V_DDO/2
100
tjit(cc)
Cycle-to-Cycle
Jitter; NOTE 4
Different Frequencies
on Different Banks
All Outputs at
Same Frequency
400
75
t_L
PLL Lock Time
t
Output Rise Time
R
t_F
Output Fall Time
odc
Output Duty Cycle
20% to 80%
20% to 80%
1
400
950
400
950
47
50
53
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input clock and the average feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
MHz
ps
ps
ps
ps
ps
mS
ps
ps
%
8752CY
www.icst.com/products/hiperclocks.html
6
REV. A AUGUST 19, 2002