ICS8752 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
DIV_SELB0,
DIV_SELB1
Input
Pulldown
Determines output divider values for Bank B as described in Table 3.
LVCMOS / LVTTL interface levels.
3, 4
DIV_SELA0,
DIV_SELA1
Input
Pulldown
Determines output divider values for Bank A as described in Table 3.
LVCMOS / LVTTL interface levels.
Active LOW Master Reset and output enable. When logic LOW, the
5
MR/nOE Input Pulldown internal dividers are reset. When HIGH, the Master Reset is disabled.
LVCMOS / LVTTL interface levels.
6
CLK0
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
7, 13, 17,
24, 28, 29
8
9
GND
FB_IN
CLK_SEL
Power
Input
Input
Power supply ground.
Pulldown
Feedback input to phase detector for generating clocks with "zero delay".
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 or CLK1 as phase detector
Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
10
V_DDA
Power
Analog supply pin.
11, 32
V_DD
Power
Positive supply pins.
12
CLK1
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
14, 15,
18, 19
16, 20,
21, 25
22, 23,
26, 27
QA0, QA1,
QA2, QA3
V_DDO
QB0, QB1,
QB2, QB3
Output
Power
Output
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins.
Bank B clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
30
nc
Unused
No connect.
Selects between the PLL and CLK0 or CLK1 as the input to the dividers.
31
PLL_SEL Input Pullup When HIGH selects PLL. When LOW selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
C_PD
R_OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
Output Impedance
Test Conditions
V_DDA, V_DD, V_DDO = 3.465V
Minimum
Typical
51
51
23
7
Maximum
4
Units
pF
KΩ
KΩ
pF
Ω
8752CY
www.icst.com/products/hiperclocks.html
2
REV. A AUGUST 19, 2002