ICS8752 Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
ICS8752
LOW SKEW, 1-TO-8
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS8752 is a low voltage, low skew
,&6
LVCMOS clock generator and a member of
HiPerClockS™ _{the HiPerClockS™ family of High Performance}
Clock Solutions from ICS. With output fre-
quencies up to 240MHz, the ICS8752 is targeted
for high performance clock applications. Along with a fully in-
tegrated PLL, the ICS8752 contains frequency configurable
outputs and an external feedback input for regenerating clocks
with “zero delay”.
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which reference
clock is used. The output divider values of Bank A and B are
controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
FEATURES
• Fully integrated PLL
• 8 LVCMOS outputs, 7Ω typical output impedance
• Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
• Input/Output frequency range: 18.33MHz to 240MHz
at V = 3.3V ± 5%
CC
• VCO range: 220MHz to 480MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
• Output skew: 100ps (maximum)
• Bank skew: 55ps (maximum)
• 3.3V or 2.5V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Functionally compatible with MPC952 in some applications
BLOCK DIAGRAM
PLL_SEL
FB_IN
CLK0 ₀
CLK1 ₁
CLK_SEL
DIV_SELA1
DIV_SELA0
PLL
PHASE
DETECTOR ^VCO
DIV_SELB1
DIV_SELB0
PIN ASSIGNMENT
÷2
00
1 ÷4
01
0 ^÷6
10
÷8
11
÷12
00
01
10
11
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
GND
FB_IN
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
ICS8752
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
GND
QB1
QB0
VDDO
VDDO
QA3
QA2
GND
MR/nOE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
8752CY
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 19, 2002