ICS8725 Datasheet, PDF (6/7 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
PRELIMINARY
ICS8725
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
D
D2
θ
1
32
25
24
L
2
3
E E1
E2
N
8
17
9
16
e
A _A2
ccc C
A1
D1
-C-
SEATING
PLANE
b
c
TABLE 7. PACKAGE DIMENISIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
BBA
NOMINAL
N
32
A
A1
0.05
A2
1.35
1.40
b
0.30
0.37
c
0.09
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60
e
0.80 BASIC
L
0.45
0.60
q
0°
ccc
Reference Document: JEDEC Publication 95, MS-026
MAXIMUM
1.60
0.15
1.45
0.45
0.20
0.75
7°
0.10
8725
www.icst.com/products/hiperclocks.html
REV. A MARCH 5, 2001
6