ICS8725 Datasheet, PDF (5/7 Pages) Integrated Circuit Systems – DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8725
1-TO-5
DIFFERENTIAL-TO-LVHSTL ZERO DELAY BUFFER
TABLE 5D. LVHSTL DC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VOH
Output High Voltage; NOTE 1
1.0
1.2
VOL
Output Low Voltage; NOTE 1
0
0.4
VOX
Output Crossover Voltage
40% x (VOH-VOL)
+ VOL
60% x (VOH-VOL)
+ VOL
NOTE 1: Outputs terminated with 50Ω to ground. The power dissipation of a terminated output pair is 32mW.
Units
V
V
V
TABLE 6. AC CHARACTERISTICS, VDDI=VDDA=3.3V±5%, VDDO=1.8V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX Maximum Output Frequency
500
MHz
VPP Peak-to-Peak Input Voltage
f = 500MHz
VCMR
tpLH
tpHL
t(Ø)
tsk(o)
tjit(cc)
tL
Common Mode Input Voltage
Propagation Delay,
Low-to-High
Propagation Delay,
High-to-Low
PLL Reference
Zero Delay;
NOTE 2
REF_CLK1,
nREF_CLK1
REF_CLK2,
nREF_CLK2
Output Skew; NOTE 3
Cycle-to-Cycle Jitter
PLL Lock Time
f = 500MHz
PLL_SEL=0V, 0MHz ≤ f ≤ 500MHz
PLL_SEL=0V, 0MHz ≤ f ≤ 500MHz
PLL_SEL=3.3V, fREF=TBD,
fVCO=TBD
Measured on rising edge at
VDDO/2
Measured on rising edge at
VDDO/2
TBD
TBD
-100
TBD
±100
TBD
ns
TBD
ns
100
ps
100
ps
ps
TBD
tR
Output Rise Time
TBD
TBD
ps
tF
Output Fall Time
tPW
Output Pulse Width
0MHz ≤ f ≤ 500MHz
f = 500MHz
TBD
TBD
ps
tCYCLE/2
-TBD
tCYCLE/2
tCYCLE/2
+TBD
ns
TBD
2.08
TBD
ns
tEN
Output Enable Time
TBD
ns
tDIS
Output Disable Time
TBD
ns
NOTE 1: All parameters measured at fMAX unless noted otherwise. All outputs terminated with 50Ω to VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent pairs
of cycles.
8725
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 5, 2001