ICS839893I Datasheet, PDF (6/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER

Integrated
Circuit
Systems, Inc.
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE 5A. AC CHARACTERISTICS, V_DD = V_{DDO_A} = V_{DDO_B} = V_{DDO_C} = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
f
Output Frequency
DC
OUT
f_REF
Input Frequency
DC
t_PD
Propagation Delay;NOTE 1
4.5
within bank
tsk(o) Output Skew; NOTE 2 bank-to-bank
Excludes QC
any output to QC
t_R/t_F
t_PZL, t_PZH
t_PLZ, t_PHZ
odc
Output Rise/Fall Time
Output Enable Time
Output Disable Time
Output Duty Cycle
20% to 80%
250
47
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 output crossing point.
Maximum
250
250
6.5
40
115
465
600
10
10
53
Units
MHz
MHz
ns
ps
ps
ps
ps
ns
ns
%
TABLE 5B. AC CHARACTERISTICS, V_DD = V_{DDO_A} = V_{DDO_B} = V_{DDO_C} = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f
Output Frequency
DC
OUT
f_REF
Input Frequency
DC
t_PD
Propagation Delay; NOTE 1
5
tsk(o)
Output Skew;
NOTE 2
within bank
bank-to-bank
any output to QC
Excludes QC
250
MHz
250
MHz
7
ns
40
ps
110
ps
410
ps
t_R/t_F
t_PZL, t_PZH
t_PLZ, t_PHZ
odc
Output Rise/Fall Time
Output Enable Time
Output Disable Time
Output Duty Cycle
20% to 80%
250
47
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 output crossing point.
600
ps
10
ns
10
ns
53
%
839893AYI
www.icst.com/products/hiperclocks.html
6
REV. A AUGUST 8, 2005