ICS82C404 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – Dual Programmable Graphics Frequency Generator

ICS82C404
The serial data register is exactly 24 bits long, enough to accept
the data being sent. The stop bit acts a load command that
passes the contents of the Serial Data Register into the register
indicated by the three address bits. If a stop bit is not received
after the serial register is full, and more data is sent, all data in
the register is ignored and an error issued. If correct data is
received, then the unlocking mechanism rearms, all data in the
serial data register is ignored, and an error is issued.
Programming the ICS82C404
The ICS82C404 has a wide operating range, but it is recom-
mended that it is operated within the following limits:
1 MHz < FREF < 60 MHz
200 kHz < FREF/M < 5 MHz
50 MHz < FVCO < 120 MHz
FCLK < 120 MHz
FREF=Input
Reference Frequency
M=Reference divide
3 to 129
FVCO=VCO output
frequency
FCLK=output
frequency
The frequency of the programmable oscillator FVCO is deter-
mined by the following fields:
The value of FVCO must remain between 50 MHz and
120 MHz. As a result, for output frequencies below 50 MHz,
FVCO must be brought into range. To achieve this, an output
divisor is selected by setting the values of the Mux Field (R)
as follows:
Output Divisor
R
Divisor
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Unlike the ICD’s 82C404, the ICS82C404’s VCO does not
require tuning to place it in certain ranges. The ICS82C404’s
VCO will operate from 50 MHz to 120 MHz without adjusting
the VCO gain. However, to maintain compatibility, the I bits
are programmed as in the ICD2061A.
These bits are dummy bits except for the following two cases:
Field
Index (I)
N counter value (N’)
Mux (R)
M counter value (M’)
# of Bits
4
7
3
7
Index Field (I)
I
VCLK FVCO
MCLK FVCO
1110 Turn off VCLK
50-120 MHz
1111 Mux MCLK to VLCK 50-120 MHz
Where the least significant bit is the last bit of M and the most
significant bit is the first bit of 1.
The equations used to determine the oscillator frequency are:
N=N’ + 3 M=M’+2
FVCO=Prescale • N/M • FCLK
where < M < 129 and 4 < N < 130
and prescale=2 or 4, as set in the control register
When the index field is set to 1111, VCLK is turned off and
both channels run from the same MCLK VCO. This is done in
an effort to reduce jitter, which may increase when VCOs run
at 2ⁿ multiples of one another. If the two outputs must be
multiples of one another, it is best to mux MCLK over to the
output of the VCLK VCO, and to power-down the VCLK
VCO. The multiplexed frequency will be divided down by the
correct divisor (M) and output on VCLK.
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