ICS82C404 Datasheet, PDF (3/13 Pages) Integrated Circuit Systems – Dual Programmable Graphics Frequency Generator

ICS82C404
Register Definitions
The register file consists of the following six registers:
Address
000
001
010
011
100
110
Register Addressing
Register
Definition
REG0
REG1
REG2
MREG
PWRDWN
CNTL REG
Video Clock Register 1
Video Clock Register 2
Video Clock Register 3
Memory Register
Divisor for Power-down mode
Control Register
The ICS82C404 places the three video clock registers and the
memory clock register in a known state upon power-up. The
registers are initialized based on the state of the INIT1 and
INIT0 pins at application of power to the device. The INIT pins
must ramp up with VDD if a logical 1 on either pin is required.
These input pins are internally pulled down and will default to
a logical 0 if left unconnected.
The registers are initialized as follows:
INIT1
0
0
1
1
Register Initialization
INIT0 MREG REG0 REG1
0 32.500 25.175 28.322
1 40.000 25.175 28.322
0 50.350 40.000 28.322
1 56.644 40.000 50.350
REG2
28.322
28.322
28.322
50.350
Register Selection
When the ICS82C404 is operating, the video clock output is
controlled with a combination of the SEL0, SEL1, PD, and OE
pins. The video clock is also multiplexed to an external clock
(EXTCLK) which can be selected with the EXTSEL pin. The
VCLK Selection Table shows how VCLK is selected.
VCLK Selection
OE PD EXTSEL FPMODE SEL1 SEL0 VCLK
0x
x
10
x
11
x
11
x
11
0
11
1
11
x
11
x
x
x x Tristate
x
x x Forced High
1
00
REG0
1
01
REG1
1
1 0 EXTCLK
1
1x
REG2
1
11
REG2
0
xx
REG2
As seen in the table above, OE acts to tristate the output. The
PD pin forces the VCLK signal high while powering down the
part. The EXTCLK pin will only be multiplexed in when
EXTSEL and SEL0 are logic 0 and SEL1 is a logic 1.
The memory clock outputs are controlled by PD and OE as
follows:
MCLK Selection
OE
PD
MCLK
0
x
Tristate
1
1
MREG
1
0
PWRDWN
The Clock Select pins SEL0 and SEL1 have two purposes. In
serial programming mode, these pins act as the clock and data
pins. New data bits come in on SEL1 and these bits are clocked
in by a signal on SEL0. While these pins are acquiring new
information, the VCLK signal remains unchanged. When
SEL0 and SEL1 are acting as register selects, a time-out
interval is required to determine whether the user is selecting
a new register or wants to program the part. During this initial
time-out, the VCLK signal remains at its previous frequency.
At the end of this time-out interval, a new register is selected.
A second time-out interval is required to allow the VCO to
settle to its new value. During this period of time, typically 5 ms,
the input reference signal is multiplexed to the VCLK signal.
When MCLK or the active VCLK register is being repro-
grammed, then the reference signal is multiplexed glitch-free
to the output during the first time-out interval. A second time-
out interval is also required to allow the VCO to settle. During
this period, the reference signal is multiplexed to the appropri-
ate output signal.
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