ICS82C404 Datasheet, PDF (4/13 Pages) Integrated Circuit Systems – Dual Programmable Graphics Frequency Generator

ICS82C404
Control Register Definition
The control register allows the user to adjust various internal options. The register is defined as follows:
Bit
Bit Name
9
C5
8
C4
7
C3
6
C2
5
C1
4
C0
3
NS2
2
NS1
1
NS0
Default Value
0
0
0
0
1
0
0
0
0
Description
This bit determines which power-down mode the PD pin will
implement. Power-down mode 1, C5=0, forces the MCLK signal to
be a function of the power-down register. Power-down mode 2,
C5=1, turns off the crystal and disables all outputs.
This bit determines which clock is multiplexed to VCLK during
frequency changes. C4=0 multiplexes the reference frequency to the
VCLK output. C4=1 multiplexes MCLK to the VCLK output for
applications where the graphics controller cannot run as slow as
fREF.
This bit determines the length of the time-out interval. The time-out
interval is derived from the MCLK VCO. If this VCO is
programmed to certain extremes, the time-out interval maybe too
short. C3=0, normal time-out. C3=1, doubled time-out interval.
Reserved, must be set to 0.
This bit adjusts the duty cycle. C1=0 causes a 1ns decrease in
output high time. C1=1 causes no adjustment. If the load
capacitance is high, the adjustment can bring the duty cycle closer
to 50%.
Reserved, must be set to 0.
Acts on register 2. NS2=0 prescales the N counter by 2.
NS2=1 prescales the P counter value to 4.
Acts on register 1. NS1=0 prescales the N counter by 2.
NS1=1 prescales the P counter value to 4.
Acts on register 0. NS0=0 prescales the P counter by 2.
NS0=1 prescales the P counter value to 4.
4